Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic

ABSTRACT

An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.

CROSS-REFERENCED APPLICATIONS

This application relates to co-pending U.S. patent application entitled “DEEP POWER SAVING BY DISABLING CLOCK DISTRIBUTION WITHOUT SEPARATE CLOCK DISTRIBUTION FOR POWER MANAGEMENT LOGIC” (Docket No. AUS920040879US1), filed concurrently herewith.

FIELD OF THE INVENTION

The present invention relates generally to clocking distribution, and more particularly, to clock distribution gating in a microprocessor.

DESCRIPTION OF THE RELATED ART

In conventional microprocessors, power consumption control has been evolving. Within microprocessors, there are three types of phenomenon that result in power consumption: direct current (DC) leakage, the clock, and alternating current (AC) usage. DC leakage is a product of the devices themselves losing charge when the system is powered. For example, thin film capacitors within a microprocessor will lose charge due to a leakage current. The clocking distribution system, mesh, or tree consumes power due the constant toggling that occurs, and the AC usage is the switching power required for active switching of the logic in the microprocessor.

Because of temperature requirements, limitations of power sources, limitations of the device, as well as other factors, there is a constant strived for a reduction in the power consumption of the microprocessors. These power reduction solutions have taken many different forms. For example, disengaging entire sections of logic on the microprocessor when not in use for extended periods of time is often employed. Also, improving the quality with which the microprocessors are manufactured is employed.

However, several techniques have been employed to reduce power consumption by the clocking distribution system. The clocking distribution system can often consume 15% or more of the total chip power. Therefore, it would be desirable to gate off the clocking distribution when the processor is in a deep power saving mode. However, pervasive logic controlling the gating of the clock distribution requires a clock to operate. Some conventional solutions utilize a separate clock for the control logic so that the control logic functions while the main clock distribution is gated off.

Having a separate clock for the control logic, however, has several drawbacks. Designing such a clocking system is difficult, requiring many man-hours. Control logic is limited to the separate clock distribution physical boundary, making integration difficult. Additionally, the separate clock distribution may be asynchronous to the main clock mesh, creating difficulty for signals crossing the synchronous-asynchronous boundary.

Therefore, there is a need for a method and/or apparatus for reducing power consumption by a clock distribution system the addresses at least some of the problems associated with conventional solutions.

SUMMARY OF THE INVENTION

The present invention provides a method and a computer program for disabling clock distribution and gating a Phased Locked Loop (PLL) while a processor is in power savings mode. A plurality of power mode signals is first generated. Then, based on the plurality of power mode signals, the PLL is gated.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram depicting a chip that includes clock gating; and

FIG. 2 is a timing diagram depicting the operation of the clock gating circuitry.

DETAILED DESCRIPTION

In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning network communications, electro-magnetic signaling techniques, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the understanding of persons of ordinary skill in the relevant art.

It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combinations thereof. In a preferred embodiment, however, the functions are performed by a processor such as a computer or an electronic data processor in accordance with code such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.

Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a block diagram depicting a chip that includes clock gating. The chip 100 comprises a chip IO 102, a system for receiving the clocking signals 104, pervasive logic 106 within the system 104, a NAND gates 108, an AND gate 116, a phased locked loop (PLL) 114, a lock detector 110, and an inverter 112.

For the chip 100 to operate, the PLL 114 generates a clocking signal for the system 104. The PLL 114 receives a reference clock signal (REF_CLK) through the communication channel 134 to generate a clocking signal. The PLL 114 then outputs an output signal (PLL_OUT) through the communication channel 130. Then, when conditions are normal and the PLL 114 is in phase/frequency lock, the AND gate 116 receives PLL_OUT and outputs a clock signal (CLK) to the system 104 through the communication channel 132.

However, to gate off CLK when the system is not is in power save mode, the PLL 114 is disabled. The chip IO 102 provides a power save mode acknowledge signal (PSM_ACK) through the communication channel 118 to the pervasive logic 106 and the NAND gate 108. The pervasive logic 106 then provides a PLL disable (PLL_DISABLE) to the NAND gate 108 through the communication channel 120. The output of the NAND gate 108 (PLL_EN) is then transmitted to the PLL 114 through the communication channel 122. If both PSM_ACK and PLL_DISABLE are logic high, then PLL_EN transitions to logic low, disabling the PLL 114.

A problem with deactivating the PLL 114 is the fact that the PLL 114 has to reach phase/frequency lock for proper CLK signal to reach the system 104. When the PLL 114 is reactivated, the PLL_OUT is also transmitted to the lock detector 110 through the communication channel 130. The output of the lock detector (LOCK) 124 is transmitted to the inverter 112 through the communication channel 124, and the inverted LOCK signal is relayed to the AND gate 116 through communication channel 128. When the PLL achieves phase/frequency lock the inverted LOCK signal transitions to logic high. Hence, the AND gate 116 prevents transmission of the CLK signal until phase/frequency lock is achieved.

A timing diagram, however, can be employed to better illustrate the functionality of the chip 100. Referring to FIG. 2 of the drawings, the reference numeral 200 generally designates a timing diagram depicting the operation of the clock gating circuitry.

At to, the PLL_OUT and CLK are normal. However, at t₁, PSM_ACK transitions to logic high. The transition of PSM_ACK to logic high, though, is not enough to disable the PLL 114. Then at t₂, the PLL_DISABLE transitions to logic high. Thus, at t₂, the PLL 114 is disabled and transitions out of phase/frequency lock.

To restart PLL operation, PSM_ACK transitions back to logic low at t₃. Since PSM_ACK has transitioned to logic low, the PLL 114 is enabled once again. However, the PLL 114 does not instantaneously achieve phase/frequency lock. A short period of time is usually required for the PLL 114 to achieve phase/frequency lock. Therefore, between t₃ and t₄, the PLL 114 is attempting to achieve phase/frequency lock. At t₄, lock is achieved, evidenced by LOCK transitioning back to logic high; thus, the CLK begins to transmit normally again.

Specifically, the operation of the clock gating system is employed during a power save mode. Within this mode the clock distribution is shut down. Then, reactivation occurs as a result of an external handshake signal(s) that “wakes up” the processor. These handshake signals are level sensitive signals that are monitored while the processor is in power saving mode. Within the configuration of the chip 100 of FIG. 1, the handshake signals are monitored with static (combinational) logic instead of a separate clock distribution. Therefore, clock distribution that is not utilized can be disabled without having to employ a separate clock distribution.

It is understood that the present invention can take many forms and embodiments. Accordingly, several variations may be made in the foregoing without departing from the spirit or the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying mechanisms on which these programming models can be built.

Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention. 

1. An apparatus for disabling clock distribution and gating a Phased Locked Loop (PLL) while a processor is in power savings mode, comprising: means for toggling the clock distribution to the processor; means for toggling the gating of the PLL; and means for toggling signals external to the processor to activate the processor from the power save mode; and means for using combinational logic to monitor the signals external to the processor.
 2. The apparatus of claim 1, wherein the combinational logic further comprises an AND gate.
 3. An apparatus for disabling clock distribution and gating a PLL while a processor is in power savings mode, comprising: at least one logic gate for receiving a plurality of enable signals and outputting an PLL enable (PLL_EN) to the PLL; and locking logic that is at least configured to enable the PLL to output of the PLL when the PLL has reached phase/frequency lock.
 4. The apparatus of claim 3, wherein the at least one logic gate further comprises a NAND gate.
 5. The apparatus of claim 3, wherein the locking logic further comprises: a lock detector to receive a PLL out and determine if the PLL is in phase/frequency lock; at least one logic unit that is at least configured to receive the PLL output and output from the lock detector, wherein the logic unit outputs a clocking signal to the processor.
 6. The apparatus of claim 5, wherein lock detector further comprises an inverter.
 7. The apparatus of claim 5, wherein the at least one logic unit further comprises an AND gate.
 8. The apparatus of claim 3, wherein the plurality of enable signals further comprises an PSM_ACK signal and a PLL disable (PLL_DISABLE) signal.
 9. A method for disabling clock distribution and gating a Phased Locked Loop (PLL) while a processor is in power savings mode, comprising: toggling the clock distribution to the processor; toggling the gating of the PLL; and toggling signals external to the processor to activate the processor from the power save mode; and using combinational logic to monitor the signals external to the processor.
 10. A method for disabling clock distribution and gating a Phased Locked Loop (PLL) while a processor is in power savings mode, comprising: generating a plurality of power mode signals; and gating the PLL based on the plurality of power mode signals.
 11. The method of claim 10, wherein the method further comprises generating a PLL_EN signal by NANDing the plurality of power mode signals.
 12. The method of claim 10, wherein the method further comprises: when the PLL is enabled, determining if the PLL is in phase/frequency lock; and preventing the PLL to transmit a clocking signal if the PLL is not in phase/frequency lock.
 13. The method of claim 12, wherein the step of determining further comprises employing a lock detector.
 14. The method of claim 13, wherein the step of prevent further comprises ANDing indicia of the output of the lock detector with the output of the PLL.
 15. A computer program product for disabling clock distribution and gating a Phased Locked Loop (PLL) while a processor is in power savings mode, the computer program product having a medium with a computer program embodied thereon, the computer program comprising: computer code for generating a plurality of power mode signals; and computer code for gating the PLL based on the plurality of power mode signals.
 16. The computer program product of claim 15, wherein the computer program product further comprises computer code for generating a PLL_EN signal by NANDing the plurality of power mode signals.
 17. The computer program product of claim 15, wherein the computer program product further comprises: when the PLL is enabled, computer code for determining if the PLL is in phase/frequency lock; and computer code for preventing the PLL to transmit a clocking signal if the PLL is not in phase/frequency lock.
 18. The computer program product of claim 17, wherein the computer code for determining further comprises computer code for employing a lock detector.
 19. The computer program product of claim 18, wherein the computer code for prevent further comprises computer code for ANDing indicia of the output of the lock detector with the output of the PLL. 